The US Department of War is partnering with industry and academia on an initiative to complete the design, fabrication, and hardware characterization of the mixed-signal application-specific integrated circuit (MS-ASIC) V2 and V3, enabling the low-cost chip-scale atomic clocks (LC CSAC) to achieve its size, weight, power, and cost (SWaP-C) targets for both military and commercial deployment.

Specific objectives include:

• Complete MS-ASIC V2 design, adding two high-resolution ADCs, laser servo current controller, and time interval counter macros to the V1 prototype, and submit for fabrication.
• Characterize MS-ASIC V2 hardware at the component level, verifying macro performance against design simulations and addressing any issues identified in V1 testing.
• Design MS-ASIC V3, integrating all remaining macros into a final production-ready ASIC.
• Characterize MS-ASIC V3 hardware to ensure overall functional and performance targets are met.

If you feel your organization has the technical capabilities and would like to be considered for this project, please complete the form below and upload your organization’s technical capabilities statement.

Interested Submissions Due by 8/6/26.

We encourage participation of Disadvantaged Business Enterprises (DBEs), including Minority Business Enterprises (MBEs) and Women’s Business Enterprises (WBEs).